Interposer and semiconductor package with noise suppression features

ABSTRACT

Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise.

RELATED APPLICATION

This application claims the benefit of U.S. Provisional Patent Application No. 61/565,353, filed Nov. 30, 2011, the contents of which are incorporated by reference as if set forth in its entirety.

TECHNICAL FIELD

This disclosure relates to semiconductor device packages and their components.

BACKGROUND

Integrated circuits (“ICs”) are incorporated into many electronic devices. IC packaging has evolved such that multiple ICs may be vertically stacked in so-called three-dimensional (“3D”) packages in order to save horizontal area on a printed circuit board (“PCB”). An alternative packaging technique, referred to as a 2.5D package, may use an interposer, which may be formed from a semiconductor material such as silicon, for coupling one or more semiconductor die to a PCB. A plurality of IC or other semiconductor die which may be of heterogeneous technologies, may be mounted on the interposer. In addition to being joined to the plurality of IC die, the interposer is also joined to the PCB and oftentimes to a package substrate disposed between the PCB and the interposer.

Many devices on one or more of the semiconductor die may cause electrical noise and/or create electromagnetic (“EM”) interference by emitting EM emissions. RF devices and inductors are examples of devices which can create electrical noise and electromagnetic (“EM”) interference. The noisy source such as an RF transmitter or receiver generates electric noise in the form of EM emissions that can propagate through air, or electrical noise in signals carried in conductive structures such as metal leads. The EM emissions and the noisy electrical signals carried in the conductive leads, can impact various other signals and devices in the interposer, the other semiconductor die coupled to the interposer, and various components in all parts of the package. Noisy electrical signals and EM emissions therefore present serious problems in semiconductor packaging.

BRIEF DESCRIPTION OF THE DRAWING

The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawing. It is emphasized that, according to common practice, the various features of the drawing are not necessarily to scale. On the contrary, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. Like numerals denote like features throughout the specification and drawing.

FIG. 1 is a side view of an embodiment of a package including an interposer;

FIG. 2 is a cross-sectional view of an embodiment of two semiconductor die coupled to an interposer;

FIGS. 3A and 3B are cross-sectional and plan views, respectively, of one embodiment of an interposer according to the disclosure;

FIGS. 4A, 4B and 4C are each perspective views illustrating an embodiment of an interposer according to the disclosure;

FIGS. 5A and 5B are cross-sectional and plan views, respectively, of an embodiment of an interposer according to the disclosure;

FIG. 6 is a cross-sectional view of an embodiment of an interposer according to the disclosure;

FIGS. 7A and 7B show another embodiment of an interposer according to the disclosure;

FIG. 8 is a cross-sectional view of an embodiment of an interposer according to the disclosure;

FIG. 9 is a plan view of an embodiment of an interposer according to the disclosure; and

FIG. 10 is a cross-sectional view of an embodiment of an interposer according to the disclosure.

DETAILED DESCRIPTION

The embodiments of the disclosure provide interposer structures, package assemblies including interposers, and couplings between interposers and semiconductor die, designed to isolate electromagnetic emission and other electrical noise by shielding the electromagnetic emission and other electrical noise from other electrical signals.

FIG. 1 shows an embodiment of a semiconductor packaging arrangement. Interposer 2 is disposed between semiconductor die 4 and 6, and PCB (printed circuit board) 8. More particularly, semiconductor die 4 and 6 are joined to first surface 10 of interposer 2 and opposed second surface 12 of interposer 2 faces PCB 8 and is directly joined to package substrate 16.

Package substrate 16 is joined to PCB 8 by solder balls 18 and to interposer 2 by solder bumps 20 in the illustrated embodiment. Solder balls 24 join interposer 2 to semiconductor die 4 and 6. Solder balls are referred to broadly as such, but need not be completely “ball shaped” as in the illustrated embodiments. Solder balls are alternatively referred to as solder bumps and take on various shapes in various embodiments. Solder balls physically join the respective components together and electrically couple electronic features of the respective components together.

Solder balls 18 have a size of about 200-300 um in one embodiment and are BGA-type solder balls in one embodiment. A ball grid array (BGA) is a type of surface-mount packaging used for integrated circuits and BGA solder balls are the type and size of solder balls commonly used in BGA applications and are known in the art. Solder balls 18 are sized differently in other exemplary embodiments. Solder bumps 20 are about 50-150 um in diameter in one embodiment, but are sized differently in other exemplary embodiments. Interposer 2 may include through-silicon vias (“TSVs”) that extend essentially from first surface 10 to second surface 12, although TSV's that extend completely through interposer 2 are not shown in the illustrated embodiment. TSV 26 is exemplary and extends from solder bump 20 to an electrical lead coupled to solder bump 24. This configuration is also exemplary. The layout shown in FIG. 1 is intended to be exemplary only and to illustrate an embodiment of an interposer included within a package that also includes PCB 8 and semiconductor die 4 and 6. In other embodiments, package substrate 16 is not used, and in other embodiments, additional semiconductor die and other components are coupled to interposer 2.

The various interposer embodiments described herein may be utilized in the exemplary package arrangement setting of FIG. 1 or in various other arrangements.

In one embodiment, interposer 2 includes a substrate body made of silicon. In another embodiment, interposer 2 includes a substrate body made of silicon-glass or other suitable materials commonly used in the semiconductor art. Interposer 2 includes a thickness suitable to meet the requirements of the specific packaging application intended.

FIG. 2 is a cross-sectional view showing an arrangement of interposer 30 and two semiconductor die 32 and 34. Interposer 30 is as the previously described interposer 2. Interposer 30 includes substrate body 36 formed of various suitable materials such as but not limited to silicon, glass-silicon and other suitable substrate materials commonly used in the semiconductor art. Interposer 30 also includes multiple conductive layers 38 separated by dielectric layers 40 which are formed of various suitable dielectric materials. Interposer 30 also includes TSVs 42 coupled to conductive layers 38 and solder balls 44 for coupling to further components in various exemplary embodiments. Solder balls 44 have a size of about 200-300 um in one embodiment and a size of about 50-150 um in another embodiment, but are sized differently in other exemplary embodiments. Semiconductor die 32 is formed of suitable substrate material and includes circuitry thereon. Semiconductor die 32 is an integrated circuit in one embodiment but may be any of various other semiconductor devices in various other embodiments. Semiconductor die 32 a P-type substrate that include N-well regions 48 and deep N-well region (“DNW”) 50 in the illustrated embodiment, but this is exemplary only. In one embodiment, semiconductor die 32 is a GPS (global positioning sensor) die that sends and receives RF signals and includes in its circuitry EM (electromagnetic) emission source 55. EM emission source 55 is an antenna in one embodiment. In another embodiment, EM emission source 55 is a an RF receiver or an RF transmitter on a GPS (global positioning sensor) chip. In yet another embodiment, EM emission source 55 is an inductor, but EM emission source may be various other circuit elements that create EM emissions in other embodiments.

EM emissions 56 are indicated by arrows that show EM emissions propagating through air and reaching semiconductor die 34. EM emissions 56 may adversely affect circuitry, signals and devices on semiconductor die 34 or other signals or features of interposer 30 or of components coupled to interposer 30. In other embodiments, semiconductor die 32 includes an electrical signal with electronic noise that is coupled to interposer 30 and travels along a conductive lead formed in interposer 30. The electrical signal with electrical noise may emanate from an RF transmitter, RF receiver, antenna, inductor or other noise generating structures.

The disclosure provides embodiments of an interposer such that the interposer and/or the coupling between the interposer and other components of the package, prevents EM emissions and electrical noise from adversely affecting other semiconductor die, i.e. the embodiments isolate the EM emissions and electrical noise, particularly for semiconductor die coupled to the same interposer. According to one embodiment illustrated in FIG. 2, the interposer and/or the coupling between the interposer and other components prevent EM emissions 56 from semiconductor die 32 from adversely affecting semiconductor die 34.

FIGS. 3A and 3B represent cross-sectional and plan views of an interposer embodiment according to the disclosure. Interposer 30 includes substrate body 36 with TSVs 42 and solder balls 44. These features are exemplary only. Interposer 30 also includes multiple conductive layers 38 with dielectric layers 40 between the conductive layers 38. The four conductive layers 38 in the illustrated embodiment are exemplary, and in other embodiments, different numbers of conductive layers may be included. Conductive layers 38 are formed of aluminum in one embodiment and conductive layers 38 are formed of copper in another embodiment. In other exemplary embodiments, conductive layers 38 are formed of alloys of aluminum or copper or various other suitable conductive materials. In other embodiments, conductive layers 38 are formed of semiconductor materials such as polysilicon but are referred to collectively as conductive layers 38. Various suitable dielectric materials used in the semiconductor art are used as dielectric layers 40.

Semiconductor the 32 includes EM emission source 55 which is shown schematically in FIG. 3A and represents an electronic device feature that generates EM emission. EM emission source 55 is an antenna in one embodiment. In another embodiment, EM emission source 55 is an RF receiver or an RF transmitter on a GPS (global positioning sensor) chip. In another embodiment, EM emission source 55 is an inductor, but may be various other circuit elements that create EM emissions in other embodiments. In one embodiment, semiconductor die 32 is a GPS die that receives and transmits radio signals. In another embodiment, semiconductor die 32 is a baseband die. Semiconductor die 32 represents any of various other integrated circuit or other semiconductor devices that have an EM emission source.

Referring to both FIGS. 3A and 3B, semiconductor die 32 is coupled to interposer 30 by strips of rows of solder bumps. FIG. 3B shows four exemplary strips, one each along the outer portions of the north, south, east and west sections of semiconductor die 32.

Each strip 60 includes at least two rows of solder balls joining semiconductor die 32 to interposer 30, and the rows are parallel in the exemplary embodiment of FIG. 3B.

In some embodiments, the strips 60 of solder balls surround the region including EM emission source 55 when semiconductor die 32 is joined to interposer 30.

Strips 60 each include inner row 62 of solder balls. Each strip 60 also includes at least another row of solder balls in addition to inner row 62 in one embodiment. In one embodiment, a second parallel row of solder balls consists of solder balls 64 (indicated by dashed lines in FIG. 3B) and in another embodiment, a second parallel row of solder bumps is indicated by solder balls 66 (indicated by dashed lines in FIG. 3B). In one embodiment, strip 60 includes three parallel rows of solder balls. Each of solder balls 64 and 66 are shown in dashed lines to indicate that either or both of the parallel rows of solder balls may be used in conjunction with parallel row 62 of solder balls.

In the illustrated embodiment of FIG. 3A, inner row 62 of solder bails 58 includes two stacked solder balls 58 and outer row 70 also includes two stacked solder balls 58. This is exemplary. Outer row 70 may be indicative of either of the rows of solder balls 64 and 66 shown in FIG. 3B or of another non-parallel row. In other embodiments, the rows of solder balls may include only a single solder ball joining semiconductor die 32 to interposer 30.

Solder balls 58 are referred to broadly as such, but need not be completely “ball shaped” as in the illustrated embodiment. Solder balls 58 are alternatively described as solder bumps and take on various shapes in various embodiments. Solder balls 58 are formed of any of various suitable solder materials used in the packaging art. In one embodiment, solder balls 58 are round and include a diameter of about 15-30 um but various other sizes are used in other exemplary embodiments. The pitch of the solder balls along the longitudinal direction of strips 60 is 30-60 micro-inches in one embodiment, but various other pitches are used in other exemplary embodiments. In one embodiment, the solder balls of the parallel rows of solder balls are arranged along the longitudinal direction of strip 60 such that an alternating sequence of solder balls from the different rows of solder balls are present along the longitudinal direction. This is exemplary only and other arrangements are used in other exemplary embodiments.

In some embodiments, the solder balls of strips 60 are arranged such that a solder ball is present in strip 60 along all linear locations along the length of strip 60. In some embodiments, strips 60 include an arrangement of solder balls not arranged in a series of rows but such that strip 60 is populated with a solder ball at some point across strip 60, at all linear locations along its length. When semiconductor die 32 is joined to interposer 30, the region surrounding EM emission source 55 has a solder ball positioned between EM emission source 55 and each peripheral location of the region surrounding EM emission source 55, in one embodiment. In some embodiments, not illustrated, strips 60 intersect and completely surround the region including EM emission source 55.

FIGS. 4A-4C illustrate three additional embodiments of an interposer according to the disclosure. Like numbers denote like features throughout the specification and the interposers 74, 90 and 100, illustrated in FIGS. 4A-4C, respectively, may be assembled in a package embodiment such as shown in FIG. 1, for example. Interposers 74, 90 and 100 each include conductive layers 38 isolated from one another by dielectric layers such as described in conjunction with interposer 30, above.

FIG. 4A shows semiconductor die 32 with EM emission source 55. Solder balls 76 are suitably sized and connect semiconductor die 32 to the illustrated portion of interposer 74. The portion of interposer 74 illustrated schematically over semiconductor die 32 is coupled to semiconductor die 32 such that the illustrated portion of interposer 74 is positioned over EM emission source 55. Capacitor 80 is formed within the illustrated portion of interposer 74 and disposed over EM emission source 55 when interposer 74 is joined to semiconductor die 32. Capacitor 80 is a metal-oxide-metal (“MOM”) capacitor and serves two purposes in some embodiments. In some embodiments, capacitor 80 is a decoupling capacitor and also provides shielding for electromagnetic emissions emanating from EM emission source 55. In some embodiments, capacitor 80 mitigates power line ripple or otherwise decouples one part from another part of an electrical circuit formed in interposer 74. Capacitor 80 shields EM emission source 55 and prevents electromagnetic interference in other components such as components of interposer 74 (not illustrated) that are formed in dashed portion 82 of interposer 74 and in devices formed on other die or other components coupled to interposer 74. Capacitor 80 includes two electrodes 84 and 86. Each electrode 84 and 86 is a plurality of interconnected parallel digits and the parallel digits of respective plates 84 and 86 are disposed between one another in an alternating fashion in one embodiment. In one embodiment, electrodes 84 and 86 are formed of the same conductive layer of interposer 74. In another embodiment, electrodes 84 and 86 are formed of different conductive layers. According to another embodiment in which electrodes 84 and 86 are formed of different conductive layers, electrodes 84 and 86 are overlaid such that the parallel digits of electrode 84 are perpendicular to the parallel digits of electrode 86.

FIG. 4B shows semiconductor die 32 with EM emission source 55. Solder balls 76 are suitably sized and connect semiconductor die 32 to the illustrated portion of interposer 74. The portion of interposer 90 illustrated schematically over semiconductor die 32 is coupled to semiconductor die 32 such that the illustrated portion of interposer 90 is positioned over EM emission source 55. Capacitor 92 is formed within the illustrated portion of interposer 90 and disposed over EM emission source 55 when interposer 90 is joined to semiconductor die 32. Capacitor 92 is a metal plate capacitor and serves two purposes in some embodiments. In some embodiments, capacitor 92 is a decoupling capacitor and also provides shielding for electromagnetic emissions emanating from EM emission source 55. In some embodiments, capacitor 92 mitigates power line ripple or otherwise decouples other electronic components of interposer 90. Capacitor 92 shields EM emission source 55 and prevents electromagnetic interference in other components such as components of interposer 90 (not illustrated) that are formed in dashed portion 98 of interposer 90 and in devices formed in other die or other components coupled to interposer 90. Capacitor 92 includes two electrodes 94 and 96. Electrodes 94 and 96 are formed of different conductive layers of interposer 90.

FIG. 4C shows semiconductor die 32 with EM emission source 55. Solder balls 76 are suitably sized and connect semiconductor die 32 to the illustrated portion of interposer 100. The portion of interposer 100 illustrated schematically over semiconductor die 32 is coupled to semiconductor die 32 such that the illustrated portion of interposer 100 is positioned over EM emission source 55 when interposer 100 is joined to semiconductor die 32. Capacitor 102 is formed within the illustrated portion of interposer 100 and positioned over EM emission source 55. Capacitor 102 is a metal-insulator-metal (“MIM”) or metal-insulator-semiconductor (“MIS”) capacitor and serves two purposes in some embodiments. Various dielectrics are used for the capacitor dielectric. In some embodiments, capacitor 102 is a decoupling capacitor for mitigating power line ripple and also provides shielding for electromagnetic emissions emanating from EM emission source 55. Capacitor 102 prevents electromagnetic interference in other components such as components of interposer 100 (not illustrated) that are formed in dashed portion 108 of interposer 100. Capacitor 102 also prevents electromagnetic interference in other components such as other semiconductor die joined to interposer 100. Capacitor 102 includes two electrodes 106 and 104. Electrodes 104 and 106 are formed of different layers of conductive layers 38 of interposer 100. In some embodiments, one of the conductive layers 38 is a semiconductor layer such as polysilicon and serves as capacitor plate 104 or 106.

FIGS. 5A and 5B illustrate another interposer embodiment of the disclosure. FIG. 5A is a cross-sectional view of interposer 120. Interposer 120 is formed of various suitable substrate materials and includes conductive layers 122 separated by dielectric material 124. In one embodiment, various suitable metal materials such as aluminum, copper or their alloys, are used for conductive layers 122.

Conductive layers 122 are formed of suitable semiconductor material such as polysilicon, in other exemplary embodiments, but are collectively referred to hereinafter simply as conductive layers 122. Conductive layers 122 are also designated “M1,” “M2,” “M3,” and “M4”. Interposer 120 is coupled to semiconductor die 126 and 128 by solder bumps 130. Solder bumps 132 couple interposer 120 to other components such as a package substrate or PCB (not shown). Through-silicon vias (“TSVs”) 136 extend completely through interposer 120 in the illustrated embodiment. In one embodiment, semiconductor die 126 is a GPS die that sends and receives RF signals and semiconductor die 128 is a baseband die, but this is intended to be exemplary only. A “Noise Source” is indicated on M1 conductive layer 122 in the illustrated embodiment indicating a noisy electrical signal carried along at least one lead within M1 conductive layer 122. The “Noise Source” lead is coupled to any of various sources of electrical noise such as may be contained in semiconductor die 126 or 128. M4 conductive layer 122 is also identified as “Signal Source” in the illustrated embodiment and represents a signal carried along a lead formed from M4 conductive layer 122 and which is desirably shielded from the electrical noise of the “Noise Source” electrical lead of M1 conductive layer 122, by a shield structure. The shield structure is formed of at least M2 conductive layer 122 and M3 conductive layer 122 such as shown in FIG. 5B. The designation of a lead within M1 conductive layer 122 as “Noise Source” and of a lead within M4 conductive layer 122 as “Signal Source” is exemplary only and in another embodiment, the “Noise Source” is a lead within M4 conductive layer 122 and the “Signal Source” is a lead in M1 conductive layer 122.

FIG. 5B shows shield 140 formed of portions of M2 conductive layer 122 and portions of M3 conductive layer 122. In the plan view of FIG. 5B, the shield is a continuous shield that extends continuously from top to bottom of the drawing, and shields any noise source above shield 140 from any signal source or other component below shield 140. Either or all of conductive leads 146 that are formed of M1 conductive layer 122 may be a noise source and the noise generated by the noise source is blocked from interfering with a signal source or other components beneath shield 140. Portions of M2 conductive layer 122, which are disposed above M3 conductive layer 122, are coupled to the portions of M3 conductive layer 122 by means of vias, contacts or other connective structures to provide a solid shield such that there is no dielectric path through shield 140. The connective structures are formed of suitable metal or semiconductor materials. An embodiment showing such interconnections is shown in FIG. 6. Still referring to FIG. 5B, shield 140 is formed of materials that absorb or block electrical noise and therefore any electrical noise from a conductive lead 146 carrying a noisy signal would have to go completely around shield 140 to affect a signal being disposed below shield 140, e.g. the Signal Source shown in FIG. 5A.

FIG. 6 is cross-sectional view showing an embodiment of an exemplary shield and illustrates the solid, continuous nature of shield 162, such qualities also applicable to shield 140 shown in FIG. 5B. Shield 162 is included with an interposer according to an embodiment of the disclosure. More particularly, shield 162 is included within dielectric layers formed over a body substrate of an interposer according to an embodiment of the disclosure.

FIG. 6 is a cross-sectional view taken along a direction transverse to the longitudinal direction of interposer, i.e., transverse to the signal carrying direction of the interposer, and shows conductive leads 150 which are formed of an upper conductive layer in one embodiment and extend in and out of the plane of the drawing page. Conductive leads 152 are formed from a subjacent conductive layer. In one embodiment, one or all of conductive leads 150 carries a noisy signal and conductive leads 152 carry another signal desired to be shielded from electrical noise and EM emissions such as may emanate from one or more of conductive leads 150. In another embodiment, the roles of conductive leads 150 and 152 are reversed. Blocking segments 154 and 156 are each formed from a further layer which may be a conductive layer as described above in various embodiments. Blocking segments 154 are coupled to blocking segments 156 by contact structures 158. Contact structures 158 are formed of conductive materials such as metals or semiconductor material in various embodiments.

The lateral dimension 160 of shield 162 formed of blocking segments 154, blocking segments 156 and contact structures 158 is chosen to be sufficiently large such that any noise in the form of EM emission radiation or other electrical noise would have to travel a substantial distance from conductive lead 150 and around shield 162 in order to reach conductive lead 152 and would advantageously become essentially dissipated before reaching conductive lead 152. Shield 162 prevents EM emissions such as EM emissions 164 from travelling through shield 162. In one embodiment, lateral dimension 160 extends substantially completely across the interposer. In some embodiments, lateral dimension 160 represents at least a majority of the width of the interposer that contains shield 162. In one embodiment, lateral dimension 160 is a dimension at least about fifteen to twenty times as great as a width of conductive lead 150. These are exemplary only. It should be understood that lateral dimension 160 of shield 162 is chosen in conjunction with the location of the noisy signals and the signal sources or other components desired to be shielded from noise, such that any EM emissions or other noise from the noisy source would have to travel completely around shield 162 and be substantially dissipated by the time it reaches the signal source of interest. In some embodiments, either or both of blocking segments 154 and 156 are grounded. In one embodiment, lower conductive leads 152 are formed of a lower conductive layer, blocking segments 156 and 154 are formed of intermediate conductive layers, and conductive leads 150 are formed of an upper conductive layer.

FIGS. 7A and 7B show another embodiment of a shield contained within an interposer according to another embodiment of the disclosure. FIG. 7A is a top view of shield 170 that is disposed beneath conductive leads 146. Conductive leads 146 may be formed of an upper conductive layer such as M1 conductive layer 122 shown in FIG. 5A. In one embodiment, one or all of conductive leads 146 carries a noisy signal and one or more further conductive leads disposed beneath shield 170 carries another signal and is desired to be shielded from electrical noise and EM emissions. Shield 170 is formed of segments of conductive material coupled together. FIG. 7B shows two exemplary checkerboard patterns. Upper checkerboard pattern 174 is formed of a conductive or semiconductor layer and lower checkerboard pattern 176 is also formed of a conductive or semiconductor layer. In one embodiment, upper checkerboard pattern 174 is formed of segments of M2 conductive layer 122 shown in FIG. 5A, lower checkerboard pattern 176 is formed of segments of M3 conductive layer 122 shown in FIG. 5A and conductive leads 146 are formed of portions of M1 conductive layer 122 shown in FIG. 5A. Upper and lower checkerboard patterns 174 and 176 are overlaid to combine to form shield 170 shown in FIG. 7A. When viewed from above, shield 170 is a continuous member formed of a solid uninterrupted pattern formed by the overlaid and interconnected checkerboard patterns. The segments of upper checkerboard pattern 174 are coupled to the segments of lower checkerboard pattern 176 by a series of contacts or vias, not visible in FIG. 7A. Shield 170 is therefore a substantially solid member that prevents noise from a noise source disposed above shield 170 from affecting a signal source disposed below shield 170. Either or all of conductive leads 146 may be a signal source or a noise source. With upper checkerboard pattern 174 coupled to lower checkerboard pattern 176 to form a solid shield 170, there are no dielectric openings that extend through shield 170.

FIG. 8 is a cross-sectional view taken along a direction transverse to the longitudinal direction of an interposer, i.e., transverse to the signal carrying direction of the interposer, and shows conductive leads 182 which are formed of an upper conductive layer in one embodiment. Shield 180 extends along the longitudinal direction of conductive leads 182 and 184 which extend into and out of the plane of the drawing page. Shield 180 is positioned between upper conductive leads 182 and lower conductive leads 184. Shield 180 is formed of segments 186 of an upper layer, segments 188 of a lower layer and contact structures 190 which join upper segments 186 to lower segments 188. Shield 180 is sized to include a dimension suitably large such that any EM emissions or other electrical noise from one of the conductive leads of 182, e.g. EM emissions 192 must travel a significantly long distance and be substantially dissipated before reaching conductive leads 184, or vice versa.

FIG. 9 illustrates another embodiment of a shield according to the disclosure. FIG. 9 is a top view that shows shield 194 including blocking portions 196 and 198. Blocking portions 196 and 198 are joined together such that shield 194 is a solid structure. Conductive leads 200 are disposed above shield 194 and further conductive leads disposed beneath shield 194 are designated by dashed lines 204. In one embodiment, one or all of conductive leads 200, which may be disposed above shield 194, carries a noisy signal and further conductive leads disposed beneath shield 194 carry another signal and are desired to be shielded from electrical noise and EM emissions such as from one or more of conductive leads 200. Shield 194 is sized to prevent EM emissions from conductive leads 200 from interfering with signals carried in conductive leads 204. In one embodiment, blocking portions 198 and 200 are formed of two intermediate conductive or semiconductor layers joined together by contacts and/ or vias. In one embodiment, shield 194 may be at least fifteen to twenty times as wide as width 210 of conductive leads 200,

FIG. 10 shows another embodiment of shields formed within an interposer according to the disclosure. More particularly, shields 222 are included within dielectric layers formed over a substrate body of an interposer according to an embodiment of the disclosure. FIG. 10 is a cross-sectional view taken along a direction transverse to the longitudinal direction of an interposer, i.e., transverse to the signal carrying direction of the interposer, and shows conductive leads 220. Shields 222 include upper segments formed of upper layer 224 which is a conductive layer in various embodiments, segments of intermediate layer 226, which is a conductive material in various embodiments, and segments of lower layer 228 which is a conductive layer in various embodiments. As previously defined, conductive layers that include upper layer 224, intermediate layer 226 and lower layer 228 may be formed of suitable metals or semiconductor materials in various exemplary embodiments. The layers are coupled together by contact structures 230 and 232.

Shields 222 are formed within dielectric material 234, which is also present between conductive leads 220 and shields 222, and is disposed over a substrate body. Conductive leads 220 are signal sources, with conductive leads 242 being a source of electrical noise in one embodiment. In another embodiment, conductive leads 242 are signal sources, with conductive leads 220 being noise sources. Shields 222 substantially surround respective conductive leads 220 and shield conductive leads 220 from conductive leads 242 and vice versa. In one embodiment, layers 224, 226, 228 and 242 are successive layers of metals, other conductive materials or semiconductor materials disposed within a dielectric such as dielectric 234 in an interposer. Either or all of conductive layers 224, 226 and 228 are coupled to ground in one embodiment and serve as ground shields.

The structures shown in cross-sections in FIGS. 6, 8 and 10 are exemplary. FIG. 10 illustrates an embodiment in which conductive layers form a shield that completely surrounds a conductive lead such that no dielectric paths exist between the surrounded conductive lead and any electrical noise such as EM emissions that may be present outside the shield, or vice versa. FIGS. 6 and 8 illustrate embodiments with solid continuous shields that include no dielectric openings therethrough. The various shield embodiments of the disclosure utilize various numbers of layers of metal and semiconductor materials. Each of these arrangements is exemplary and various other embodiments include arrangements that combine features of the exemplary shields illustrated, e.g. a surrounding shield such as shield 222 in FIG. 10 may be used in combination with a wide shield such as shield 180 of FIG. 8.

According to one embodiment, an interposer for connecting a semiconductor die to a printed circuit board is provided. The interposer includes a body having opposed first and second surfaces. A facing surface of the semiconductor die is joined to the first surface of the interposer by at least a strip of multiple rows of solder balls that are disposed on, and extend along, the facing surface on outer portions of the semiconductor die.

According to another embodiment, a semiconductor package includes a printed circuit board; a semiconductor die; and an interposer interposed between the printed circuit board and the semiconductor die, the interposer having first and second opposed surfaces. The first surface is coupled to the printed circuit board. A facing surface of the semiconductor die is joined to the second surface of the interposer by at least a strip of parallel rows of solder balls that extend along the facing surface on outer portions of the semiconductor die.

According to another embodiment, an interposer for connecting a semiconductor die to a printed circuit board is provided. The interposer includes a body having opposed first and second surfaces and a plurality of conductive layers therein. The semiconductor die is joined to the first surface of the interposer at a first location, the first location comprising a geometric portion of the interposer that faces the semiconductor die. The interposer includes an internal electromagnetic shield in the first location, the internal electromagnetic shield being a capacitive device formed of the conductive layers.

According to another embodiment, an interposer for connecting a semiconductor die to a printed circuit board is provided. The interposer includes a body having opposed first and second surfaces; a plurality of conductive layers within the interposer, wherein one of the conductive layers includes a first metal lead and a further of the conductive layers includes a second metal lead and the first metal lead is shielded from the second metal lead by a shield including at least one interposed conductive layer of the conductive layers. The first metal lead extends along a longitudinal direction of the interposer and the shield extends continuously laterally across at least a majority of a transverse direction of the interposer between the first and second metal leads. The conductive layers are formed of metal materials or semiconductor materials.

According to another embodiment, an interposer for connecting a semiconductor die to a printed circuit board is provided. The interposer includes a substrate body; a plurality of conductive layers disposed in a dielectric material on the substrate body; a first metal lead; and a shield surrounding the first metal lead, the shield including at least one of semiconductor materials, portions of the conductive layers and further metal portions.

The preceding merely illustrates the principles of the disclosure. It will thus be appreciated that those of ordinary skill in the art will be able to devise various arrangements which, although not explicitly described or shown herein, embody the principles of the disclosure and are included within its spirit and scope. Furthermore, all examples and conditional language recited herein are principally intended expressly to be only for pedagogical purposes and to aid the reader in understanding the principles of the disclosure and the concepts contributed by the inventors to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the disclosure, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents and equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.

This description of the exemplary embodiments is intended to be read in connection with the figures of the accompanying drawing, which are to be considered part of the entire written description. In the description, relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “below,” “up,” “down,” “top” and “bottom” as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) should be construed to refer to the orientation as then described or as shown in the drawing under discussion. These relative terms are for convenience of description and do not require that the apparatus be constructed or operated in a particular orientation. Terms concerning attachments, coupling and the like, such as “connected” and “interconnected,” refer to a relationship wherein structures are secured or attached to one another either directly or indirectly through intervening structures, as well as both movable or rigid attachments or relationships, unless expressly described otherwise.

Although the disclosure has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended claims should be construed broadly, to include other variants and embodiments of the disclosure, which may be made by those of ordinary skill in the art without departing from the scope and range of equivalents of the disclosure. 

What is claimed is:
 1. An interposer for connecting a semiconductor die to a printed circuit board, said interposer comprising: a body having opposed first and second surfaces, wherein a facing surface of said semiconductor die is joined to said first surface of said interposer by at least a strip of multiple rows of solder balls that are disposed on, and extend along, said facing surface on outer portions of said semiconductor die,
 2. The interposer as in claim 1, wherein said at least a strip comprises strips extending peripherally around a region including an EM emission source disposed on said facing surface of said semiconductor die and said rows of solder balls are parallel.
 3. The interposer as in claim 2, wherein said EM emission source comprises an RF device, said RF device being at least one of an RF transmitter and an RF receiver.
 4. The interposer as in claim 1, wherein said rows of solder balls include three parallel rows.
 5. The interposer as in claim 1, wherein said rows of solder balls include two parallel rows and a repeating sequence of said solder balls along a longitudinal direction of said strips includes solder balls from alternating parallel rows of said two rows.
 6. The interposer as in claim 1, further comprising a further semiconductor die laterally spaced from said semiconductor die and further joined to said first surface of said interposer.
 7. The interposer as in claim 1, wherein each of said multiple rows of solder balls includes pairs of stacked solder balls arranged in said rows, each said pair interposed between said facing surface of said semiconductor die and said first surface of said interposer.
 8. The interposer as in claim 1, wherein, at each lengthwise location along a length of said strip, at least a portion of one of said solder balls is present at a location across a width of said strip.
 9. A semiconductor package comprising: a printed circuit board; a semiconductor die; and an interposer interposed between said printed circuit board and said semiconductor die, said interposer having first and second opposed surfaces; and said first surface coupled to said printed circuit board and wherein a facing surface of said semiconductor die is joined to said second surface of said interposer by at least a strip of multiple rows of solder balls that extend along said facing surface on outer portions of said semiconductor die.
 10. The semiconductor package as in claim 9, wherein said multiple rows are parallel rows and further comprising a plurality of vias extending through said interposer from said first surface to said second surface and a package substrate interposed between said first surface of said interposer and said printed circuit board.
 11. The semiconductor package as in claim 9, wherein said at least a strip comprises strips extending peripherally around a region of said facing surface of said semiconductor die, each said strip including two of said rows, and wherein a repeating sequence of said solder balls along a longitudinal direction of each of said strips includes solder balls from alternating rows of said two rows.
 12. The semiconductor package as in claim 11, wherein said region includes an EM emission source.
 13. An interposer for connecting a semiconductor die to a printed circuit board, said interposer comprising: a body having opposed first and second surfaces and a plurality of conductive layers therein, said semiconductor die joined to said first surface of said interposer at a first location, said first location comprising a geometric portion of said interposer that faces said semiconductor die and wherein said interposer includes an internal electromagnetic shield in said first location, said internal electromagnetic shield being a capacitive device formed of said conductive layers.
 14. The interposer as in claim 13, wherein said plurality of conductive layers comprise metal layers and said capacitive device is a metal plate capacitor formed of overlying metal plates formed from said metal layers.
 15. The interposer as in claim 13, wherein said plurality of conductive layers comprise metal layers and said capacitive device is a metal-insulator-metal (MIM) capacitor with electrodes formed of said metal layers.
 16. The interposer as in claim 13, wherein said plurality of conductive layers includes at least one metal layer and at least one semiconductor layer and said capacitive device is a metal-oxide-semiconductor (MOS) capacitor having one capacitor plate formed of said at least one semiconductor layer and a further capacitor plate formed of said at least one metal layer.
 17. The interposer as in claim 13, wherein said plurality of conductive layers comprise metal layers and said capacitive device is a metal-oxide-metal (MOM) capacitor formed of two capacitor electrodes, each including a plurality of digital leads of at least one of said metal layers.
 18. The interposer as in claim 13, wherein said plurality of conductive layers comprise metal layers and said capacitive device is a metal-oxide-metal (MOM) capacitor formed of two capacitor electrodes formed of a first metal layer of said plurality of metal layers, a first of said two capacitor electrodes including a plurality of first parallel leads coupled together and a second of said two capacitor electrodes including a plurality of second parallel leads coupled together, said first parallel leads disposed alternatingly between adjacent ones of said second parallel leads.
 19. The interposer as in claim 13, wherein said plurality of conductive layers comprise metal layers and said capacitive device is a metal-oxide-metal (MOM) capacitor formed of two capacitor electrodes, a first of said two capacitor electrodes formed of a first metal layer of said metal layers and including a plurality of first parallel leads coupled together and a second of said two capacitor electrodes formed of a second metal layer of said metal layers and including a plurality of second parallel leads coupled together, said first and second parallel leads disposed perpendicular to one another.
 20. The interposer as in claim 13, wherein said interposer includes an electrical circuit therein and said capacitive device is a decoupling capacitor that decouples one part of said electrical circuit from another part of said electrical circuit.
 21. An interposer for connecting a semiconductor die to a printed circuit board, said interposer comprising: a substrate body having opposed first and second surfaces; a plurality of conductive layers disposed in a dielectric material on said substrate body, wherein one of said conductive layers includes a first metal lead and a further of said conductive layers includes a second metal lead, wherein said first metal lead is shielded from said second metal lead by a shield including portions of at least one interposed conductive layer of said conductive layers; said first metal lead extending along a longitudinal direction of said interposer and said shield extending continuously laterally across at least a majority of a transverse direction of said interposer between said first and second metal leads; and wherein said conductive layers are formed of metal materials or semiconductor materials.
 22. The interposer as in claim 21, further comprising a plurality of vias extending through said interposer from said first surface to said second surface; and wherein each said interposed conductive layer is coupled to ground.
 23. The interposer as in claim 21, wherein said shield includes a plurality of said interposed conductive layers coupled together by conductive contacts or semiconductor contacts.
 24. The interposer as in claim 21, wherein said shield forms a continuous member of said metal materials or semiconductor materials, and there is no dielectric path from said first metal lead to said second metal lead through said shield.
 25. The interposer as in claim 21, wherein said first metal lead carries a noisy electrical signal and said second metal lead carries a further signal and said shield shields said second metal lead from electrical noise from said first metal lead.
 26. The interposer as in claim 21, wherein said first metal lead is disposed above said shield and said shield includes a width at least twenty times as wide as a width of said first metal lead.
 27. The interposer as in claim 21, wherein said shield is formed of at least first and second interposed conductive layers of said interposed conductive layers, each of said first and second interposed layers formed in a checkerboard pattern and overlaid such that said overlaid checkerboard patterns produce a solid uninterrupted pattern as viewed from above said plurality of conductive layers.
 28. The interposer as in claim 27, wherein said first and second interposed conductive layers are coupled together such that said shield is a continuous solid body.
 29. The interposer as in claim 27, wherein said first interposed conductive layer comprises metal and said second interposed conductive layer comprises polysilicon.
 30. An interposer for connecting a semiconductor die to a printed circuit board, said interposer comprising: a substrate body; a plurality of conductive layers disposed in a dielectric material on said substrate body; a first metal lead; and a shield surrounding said first metal lead, said shield including at least one of semiconductor materials, portions of said conductive layers and further metal portions.
 31. The interposer as in claim 30, wherein said first metal lead extends along a longitudinal direction of said interposer and is formed of an intermediate conductive layer of said plurality of conductive layers and said shield covers opposed sides and top and bottom of said first metal lead.
 32. The interposer as in claim 30, further comprising a plurality of through-silicon-vias extending through said interposer and wherein said first metal lead carries an electrical signal and is a portion of an intermediate conductive layer of said plurality of conductive layers.
 33. The interposer as in claim 32, wherein a lower portion of said shield is a portion of a lower conductive layer of said plurality of conductive layers, an upper portion of said shield is a portion of an upper conductive layer of said plurality of conductive layers and side portions of said shield include portions of said intermediate conductive layer.
 34. The interposer as in claim 33, wherein at least one of said lower portion of said shield and said upper portion of said shield is coupled to ground.
 35. The interposer as in claim 30, wherein a further of said conductive layers includes a second metal lead that is coupled to a source of electrical noise, said second metal lead disposed outside said shield.
 36. The interposer as in claim 35, wherein said interposer is coupled to a semiconductor die and wherein said second metal lead is coupled to one of an RF receiver, an RF transmitter and an inductor formed on said semiconductor die. 